A) Field of the Invention
The present invention relates to a high speed semiconductor device and its manufacture, and more particularly to a semiconductor device having a mushroom gate and its manufacture.
In this specification, “exposure” is intended to mean the concept including not only irradiation of light but also irradiation of other energy beams such as an electron beam and an X-ray beam.
B) Description of the Related Art
A mushroom gate is used as the gate of a high speed compound semiconductor transistor such as a high electron mobility transistor (HEMT) in order to reduce the resistance of the gate electrode while the gate length is made short. The mushroom gate is narrow along the current direction at the stem in contact with a semiconductor substrate and broad along the current direction at the upper head. Source and drain electrodes are formed on both sides of the mushroom gate to constitute a transistor structure.
In order to form multi-level wiring layers over a semiconductor substrate, it is necessary to form an insulating film burying the gate electrode. The material of the insulating film is inorganic insulating material such as silicon oxide and silicon nitride or organic (insulating) material. As the surface of a gate electrode is covered with the insulating film, parasitic capacitance of the gate electrode increases because a dielectric constant of the insulating film is larger than 1 which is the dielectric constant of air.
FIG. 8 is a cross sectional view showing an example of the structure of a compound semiconductor device having multi-level wiring layers. A semiconductor substrate 100 has a structure in which a functional semiconductor region is formed on an underlying substrate of GaAs or InP. A low resistance layer is formed in the upper surface layer of the semiconductor substrate 100, and a source electrode 101 and a drain electrode 102 are formed on the low resistance layer in ohmic contact therewith. The surface low resistance layer is removed in the intermediate area between the source electrode 101 and drain electrode 102 to form a recess area. On this recess area, a mushroom gate 105 is formed.
The mushroom gate 105 has a stem (hereinafter called a fine gate) which contacts the semiconductor substrate 100 and is narrow along the current direction and a head (hereinafter called an over gate) which is broad along the current direction. In order to enhance high speed operation the size of the fine gate along the current direction is made narrow, and in order to reduce the gate resistance the size of the over gate along the current direction is made broad.
If multi-level wiring layers are to be formed, a first interlayer insulating film 110 is formed burying the gate electrode 105. The first interlayer insulating film 110 covers the side walls of the fine gate of the gate electrode 105 and extends covering the upper surface of the over gate. Contact holes are formed in the first interlayer insulating film 110 and first-layer wiring patterns 112 and 113 are formed being connected to the source electrode 101 and drain electrode 102. Similarly, the gate electrode is also connected to a wiring pattern. A second interlayer insulating film 115 is formed burying the first layer wiring patterns 112 and 113. A via hole is formed in the second interlayer insulating film 115 and a second layer wiring pattern 117 is formed being electrically connected to the first layer wiring pattern.
With this gate electrode structure, the upper, lower and side surfaces of the over gate and the side surfaces of the fine gate are in contact with the interlayer insulating film 110. The parasitic capacitance of the gate electrode 105 therefore increases which is determined by the dielectric constant and the like of the interlayer insulating film. In order to reduce the parasitic capacitance of the over gate, it is desired to remove the interlayer insulating film at least under the over gate.
A lamination structure has been formed conventionally in a space surrounding the fine gate, and a partial region of the lamination structure is made hollow to reduce the parasitic capacitance of the gate electrode. Another proposal has been made in which a polyimide layer is formed burying a gate electrode, the polyimide film is removed by anisotropic etching with oxygen plasma by using the gate electrode as a mask to leave polyimide only under the over gate, thereafter an insulating film of silicon oxide, silicon nitride or the like is formed covering the gate electrode, and then the polyimide region under the over gate is removed by ashing with oxygen plasma.
It is not easy to manufacture a semiconductor device which has a high yield, a high reliability and a reduced parasitic capacitance of a mushroom gate covered with an interlayer insulating film.